1. Field of the Invention
This invention relates generally to the field of control systems and, more particularly, to control systems using data link modules communicating on a serial time division multiplex bus.
2. Description of the Related Art
Control systems employing a serial multiplex bus for controlling at least one output device by a plurality of input devices are well known. Some known control systems use software protocols, operating under the direction of a computer, in which all control signal data is conveyed in multi-bit bytes or in packets of multi-bit bytes. Examples of such software protocol control systems are the LonWorks local operating network by Echelon Company of Palo Alto, Calif.; the home automation system Consumer Electronics Bus (CEbus) by the Electronic Industry Association, the Controller Area Network (CAN) by Robert Bosch, GmbH of Stuttgart, Germany and the World Factory Implementation Protocol by the WorldFIP Committee of Research Triangle Park, N.C. Known software protocol control systems disadvantageously require multi-bit bytes, typically 16-bit bytes, for conveying only one bit of data. Although software protocol control systems are designed to convey multi-bit bytes or words, they are disadvantageously 10-100 times slower than hardware protocol systems, such as the invention, in conveying multibit words. In most software protocol control systems, the control protocol is composed of a header, the number of words in the transmission, load identification, load status and checksum. In most such systems, a minimum of six 8-bit words are needed to turn on one load. In some software protocol systems, up to three times as many bits are required.
Software protocol systems have their communication capabilities disadvantageously centralized, or lumped, in a computer that uses software to operate the control system; they disadvantageously require the computer in order to function, and therefore, if the computer malfunctions, then the control system will malfunction.
Other serial multiplex control systems use single bits of data to convey control signals and such systems have their communication capabilities distributed throughout the system, usually at each input and output location. Most of these distributed, single-bit systems have hardware protocols without any programmability. An example of this type of single-bit, hardware protocol control system is the Actuator Sensor Interface (ASI) by ASI Verein eV Geschaftsfuhrung of Odenthal, Germany. Other examples are shown and described in U.S. Pat. Nos. 4,052,566 and 4,052,567 issued Oct. 4, 1977 to MacKay; U.S. Pat. No. 4,156,112 issued May 22, 1979 to Moreland; U.S. Pat. No. 4,435,706 issued Mar. 6, 1984 to Callan; and U.S. Pat. No. 4,682,168 issued Jul. 21, 1987 to Chang, et al.
Hardware protocol systems are known to use a programmable logic controller (PLC) which is a computer programmed in ladder logic. Such systems disadvantageously require multiple lengthy cable runs interconnecting the input and output devices to a terminal. The execution speed of a PLC computer is often too slow to provide real time operation.
Most known single-bit, hardware protocol systems are not programmable; however, an example of one such system that is programmable, through firmware, is described in U.S. Pat. No. 4,808,994 issued Feb. 28, 1989 to Riley. Known programmable systems, such as that of the aforesaid patent of Riley require additional dedicated terminals on the module for acceptance of programming information.
Known single-bit, hardware protocol control systems, such as that of the aforementioned patent of Riley, multiplex frames of time which are further divided into 256 time slots, each time slot representing an address and each input and output device being associated with an address. The above described single-bit, hardware protocol systems are relatively simple compared to the software protocol systems, and they lack the capability to directly handle multi-bit words of data. The control system of the aforementioned patent of Riley can directly handle at most 2-bit words. single-bit hardware protocol control systems disadvantageously require modification by complicated additional circuitry to convey multi-bit words of data. However, the complicated additional circuitry disadvantageously restricts known modified single-bit hardware protocol systems to a fixed word length. In the prior art two channel data link modules of the aforementioned patent of Riley, the beginning address of a multi-bit word is determined by the address of one of the channels, but disadvantageously, the ending address of the multi-bit word is not selectable. The ending address is disadvantageously fixed at either eight bits after the beginning address if a host computer is used, or at sixteen bits after the beginning address if no host computer is used.
The complicated additional circuitry used with known data link modules is mounted external to a main integrated circuit on the data link module. In the aforementioned patent of Riley, the additional circuitry generates, during a part of the time frame equal to the number of bits in the multi-bit word, a clock signal in phase with a system master clock signal. The additional circuitry is required to be complicated because the integrated circuit disadvantageously lacks a terminal for bringing out a shift clock in and a shift clock out signal.
Known systems are limited to 256 input devices plus 256 output devices with each input and output device having a different address. When single-bit systems are modified with the complicated additional circuitry for multi-bit words, such as sixteen bit words, at most only sixteen words can be conveyed by the system. The multiplexing of frames permits known systems to convey more than sixteen words; however, multiplexing of frames requires still more complicated additional circuitry. In known systems, it is necessary for the additional circuitry to produce a multiplexing clock signal in phase with a master clock signal for a portion of the frame. There is no provision in known data link module integrated circuits for bringing out a synchronizing detection signal. The known data link modules also lack an external terminal on the integrated circuit of the data link module for bringing out a multiplexing clock signal. Instead, close tolerance one-shot multivibrators, prone to going off-tolerance, are used in known data link modules, and any slight mismatch of parameters can result in system failure. With known systems, external circuitry has to perform the synchronizing detection using a leading edge detection device having a discriminator that can fail to operate properly at high frequencies and an RC circuit with a time constant selected to simulate the frame period. However, the relatively expensive RC circuit is disadvantageously temperature sensitive, is not sync locked, prone to failure at higher frequencies and is expensive. Known data link modules also lack sufficient space. The above described complicated additional circuitry takes up substantial space in known data link modules.
Known data link module integrated circuits have a transistor internal to the integrated circuit for driving the data bus voltage low in order to represent a signal in negative logic. Known data bus currents are about thirty milliamperes, and known data bus voltages are about twelve volts. However, the internal transistor used for driving the data bus low in known data link module integrated circuits often fails when the data bus current and voltage becomes slightly higher than normal, such as fifty milliamperes and sixteen volts.
Control systems are used in environments such as manufacturing and assembly factories and are exposed to electromagnetic noise, static, and spikes, pulses and transient voltages (herein referred to collectively as "noise"). Known data link modules passively rely upon the lack of temporal coincidence between noise and signals to avoid noise interference. The presence of noise can cause an output device to respond at an inappropriate moment or fail to respond when the output device should do so. Solely relying upon data signals being synchronized with an edge of a clock pulse has been found insufficient to sufficiently eliminate the effect of noise on a control system.
Known data link modules have a relatively narrow operating voltage range, usually nine to thirteen volts, and it is impossible to use known data link modules with both twelve volt and the popular 24 volt systems without adding additional circuitry external to the integrated circuit for conversion of voltages.
Propagation delays and certain other conditions can produce a false output signal under certain conditions during start-up which are preferably avoided. The known systems respond to changes in an input signal occurring within a time-slot to produce false outputs. Known data link modules also continue to produce an output signal even after a loss of a master clock signal which reduces the degree of control during such conditions.
The prior art data link module of the aforementioned patent of Riley has a third output that is a logical combination of the two other outputs. The polarity of the other two outputs is selectable, but disadvantageously the polarity of the third output is not selectable independently of the polarity of the other two outputs, and as a result, sophisticated logic functions cannot be easily implemented.
Known hardware protocol, serial multiplex control systems lack circuitry to determine whether the data bus is open, or lacks continuity. Such known control systems merely check whether the data bus is shorted. Furthermore, known data link modules lack circuitry for selectively checking the continuity of a line connecting an individual module to the data bus and for selectively turning off a module in the event the data line to that module has faulted. Known control systems use the clock module to place a test pulse on the data bus during the sync period. Then, the circuitry on known clock modules determines whether the attempt at placing a test pulse on the data bus succeeded. If the attempt at placing the test pulse on the data bus failed, known control systems merely turn off the master clock; however, merely turning off the master clock does not immediately prevent output modules from continuing to produce false control signals to output devices. Furthermore, known control systems disadvantageously test the condition of the data bus only at the clock module. The test performed by the clock module on known control systems does not, and can not, determine whether a data line to an individual data link module is intact because known data link modules lack additional circuitry for receipt of the test pulse.